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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg786/adg788 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., 2.5 , 1.8 v to 5.5 v, 2.5 v triple/quad spdt switches in chip scale packages general description the adg786 and adg788 are low voltage, cmos devices comprising three independently selectable spdt (single pole, double throw) switches and four independently selectable spdt switches respectively. low power consumption and operating supply range of 1.8 v to 5.5 v and dual 2.5 v make the adg786 and adg788 ideal for battery powered, portable instruments and many other applications. all channels exhibit break-before-make switch- ing action preventing momentary shorting when switching channels. an en input on the adg786 is used to enable or disable the device. when disabled, all channels are switched off. these multiplexers are designed on an enhanced submicron process that provides low power dissipation yet gives high switch- ing speed, very low on resistance, high signal bandwidths and low leakage currents. on resistance is in the region of a few ohms, is closely matched between switches and very flat over the full signal range. these parts can operate equally well in either direction and have an input signal range which extends to the supplies. the adg786 and adg788 are available in small 20-lead chip scale packages. product highlights 1. small 20-lead 4 mm 4 mm chip scale packages (csp). 2. single/dual supply operation. the adg786 and adg788 are fully specified and guaranteed with 3 v 10% and 5 v 10% single supply rails, and 2.5 v 10% dual supply rails. 3. low on resistance (2.5 typical). 4. low power consumption (<0.01 w). 5. guaranteed break-before-make switching action. functional block diagrams s1b d1 s1a a0 s2a d2 s2b s3b d3 s3a a1 adg786 switches shown for a logic ?1? input s1a d1 s1b in1 in2 s2b d2 s2a s3a d3 s3b in3 in4 s4b d2 s4a adg788 en a2 logic a 781/461-3113 2012 features 1.8 v to 5.5 v single supply 2.5 v dual supply 2.5 on resistance 0.5 on resistance flatness 100 pa leakage currents 19 ns switching times triple spdt: adg786 quad spdt: adg788 20-lead 4 mm 4 mm chip scale packages low power consumption ttl/cmos-compatible inputs for functionally-equivalent devices in 16-lead tssop packages, see adg733/adg734 qualified for automotive applications applications data acquisition systems communication systems relay replacement audio and video switching battery-powered systems
rev. C2C adg786/adg788?specifications 1 b version ?40 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.5 typ v s = 0 v to v dd , i ds = 10 ma; 4.5 5.0 max test circuit 1 on-resistance match between 0.1 typ v s = 0 v to v dd , i ds = 10 ma channels ( r on ) 0.4 max on-resistance flatness (r flat(on) ) 0.5 typ v s = 0 v to v dd , i ds = 10 ma 1.2 max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v d = v s = 1 v, or 4.5 v; 0.1 0.5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 4 pf typ dynamic characteristics 2 t on 19 ns typ r l = 300 , c l = 35 pf; 34 ns max v s1a = 3 v, v s1b = 0 v, test circuit 4 t off 7 ns typ r l = 300 , c l = 35 pf; 12 ns max v s = 3 v, test circuit 4 adg786 t on ( en ) 20 ns typ r l = 300 , c l = 35 pf; 40 ns max v s = 3 v, test circuit 5 t off ( en ) 7 ns typ r l = 300 , c l = 35 pf; 12 ns max v s = 3 v, test circuit 5 break-before-make time delay, t d 13 ns typ r l = 300 , c l = 35 pf; 1 ns min v s = 3 v, test circuit 6 charge injection 3 pc typ v s = 2 v, r s = 0 , c l = 1 nf; test circuit 7 off isolation ?72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 9 ?3 db bandwidth 160 mhz typ r l = 50 , c l = 5 pf, test circuit 10 c s (off) 11 pf typ f = 1 mhz c d , c s (on) 34 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max notes 1 temperature range is as follows: b version: ?40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) a
rev. C3C adg786/adg788 specifications 1 b version ?40 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )6 typ v s = 0 v to v dd , i ds = 10 ma; 11 12 max test circuit 1 on-resistance match between 0.1 typ v s = 0 v to v dd , i ds = 10 ma channels ( r on ) 0.5 max on-resistance flatness (r flat(on) )3 typ v s = 0 v to v dd , i ds = 10 ma leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.3 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v s = v d = 1 v or 3 v; 0.1 0.5 na max test circuit 3 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 4 pf typ dynamic characteristics 2 t on 28 ns typ r l = 300 , c l = 35 pf; 55 ns max v s1a = 2 v, v s1b = 0 v, test circuit 4 t off 9 ns typ r l = 300 , c l = 35 pf; 16 ns max v s = 2 v, test circuit 4 adg786 t on ( en ) 29 ns typ r l = 300 , c l = 35 pf; 60 ns max v s = 2 v, test circuit 5 t off ( en ) 9 ns typ r l = 300 , c l = 35 pf; 16 ns max v s = 2 v, test circuit 5 break-before-make time delay, t d 22 ns typ r l = 300 , c l = 35 pf; 1 ns min v s = 2 v, test circuit 6 charge injection 3 pc typ v s = 1 v, r s = 0 , c l = 1 nf; test circuit 7 off isolation ?72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 9 ?3 db bandwidth 160 mhz typ r l = 50 , c l = 5 pf, test circuit 10 c s (off) 11 pf typ f = 1 mhz c d , c s (on) 34 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 0.001 a typ digital inputs = 0 v or 3.3 v 1.0 a max notes 1 temperature ranges are as follows: b version: ?40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 3 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) a
rev. C4C adg786/adg788?specifications 1 dual supply b version ?40 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 2.5 typ v s = v ss to v dd , i ds = 10 ma; 4.5 5.0 max test circuit 1 on-resistance match between 0.1 typ v s = v ss to v dd , i ds = 10 ma channels ( r on ) 0.4 max on-resistance flatness (r flat(on) ) 0.5 typ v s = v ss to v dd , i ds = 10 ma 1.2 max leakage currents v dd = +2.75 v, v ss = ?2.75 v source off leakage i s (off) 0.01 na typ v s = +2.25 v/?1.25 v, v d = ?1.25 v/+2.25 v; 0.1 0.3 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v s = v d = +2.25 v/?1.25 v, test circuit 3 0.1 0.5 na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 4 pf typ dynamic characteristics 2 t on 21 ns typ r l = 300 , c l = 35 pf; 35 ns max v s1a = 1.5 v, v s1b = 0 v, test circuit 4 t off 10 ns typ r l = 300 , c l = 35 pf; 16 ns max v s = 1.5 v, test circuit 4 adg786 t on ( en ) 21 ns typ r l = 300 , c l = 35 pf; 40 ns max v s = 1.5 v, test circuit 5 t off ( en ) 10 ns typ r l = 300 , c l = 35 pf; 16 ns max v s = 1.5 v, test circuit 5 break-before-make time delay, t d 13 ns typ r l = 300 , c l = 35 pf; 1 ns min v s = 1.5 v, test circuit 6 charge injection 5 pc typ v s = 0 v, r s = 0 , c l = 1 nf; test circuit 7 off isolation ?72 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 9 ?3 db bandwidth 160 mhz typ r l = 50 , c l = 5 pf, test circuit 10 c s (off) 11 pf typ f = 1 mhz c d , c s (on) 34 pf typ f = 1 mhz power requirements v dd = +2.75 v i dd 0.001 a typ digital inputs = 0 v or 2.75 v 1.0 a max i ss 0.001 a typ v ss = ?2.75 v 1.0 a max digital inputs = 0 v or 2.75 v notes 1 temperature range is as follows: b version: ?40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +2.5 v 10%, v ss = ?2.5 v 10%, gnd = 0 v, unless otherwise noted.) a
rev. adg786/adg788 C5C absolute maximum ratings 1 (t a = 25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 v to +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?3.5 v analog inputs 2 . . . . . . . . . . . . . . v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 2 . . . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range industrial (a, b versions) . . . . . . . . . . . . . ?40 c to +85 c storage temperature range . . . . . . . . . . . . ?65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c 20 lead csp, ja thermal impedance . . . . . . . . . . . 32 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 300 c ir reflow, peak temperature . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a, en, in, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. pin configurations nc = no connect exposed pad tied to substrate, v ss top view (not to scale) pin 1 identifier s2a s3b d3 s3a en d2 s1b s1a adg786 s2b nc nc nc v dd v ss gnd a2 a1 a0 1 2 3 4 5 6 78 910 11 12 13 14 15 16 17 18 19 20 nc d1 top view (not to scale) pin 1 identifier d1 s1b v ss gnd s2b s4b v dd s3b d3 s3a adg788 s1a in1 in4 s4a d4 d2 s2a in2 in3 nc 1 2 3 4 5 6 78 910 11 12 13 14 15 16 17 18 19 20 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg786/adg788 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device a
rev. adg786/adg788 C6C table i. adg786 truth table a2 a1 a0 en on switch x x x 1 none 0 0 0 0 d1-s1a, d2-s2a, d3-s3a 0 0 1 0 d1-s1b, d2-s2a, d3-s3a 0 1 0 0 d1-s1a, d2-s2b, d3-s3a 0 1 1 0 d1-s1b, d2-s2b, d3-s3a 1 0 0 0 d1-s1a, d2-s2a, d3-s3b 1 0 1 0 d1-s1b, d2-s2a, d3-s3b 1 1 0 0 d1-s1a, d2-s2b, d3-s3b 1 1 1 0 d1-s1b, d2-s2b, d3-s3b table ii. adg788 truth table logic switch a switch b 0 off on 1 on off v dd most positive power supply potential v ss most negative power supply in a dual supply application. in single supply applications, this should be tied to ground close to the device. i dd positive supply current i ss negative supply current gnd ground (0 v) reference s source terminal. may be an input or output d drain terminal. may be an input or output in logic control input v d (v s ) analog voltage on terminals d, s r on ohmic resistance between d and s r on on resistance match between any two channels, i.e., r on max ? r on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch ?off? i d , i s (on) channel leakage current with the switch ?on? v inl maximum input voltage for logic ?0? v inh minimum input voltage for logic ?1? i inl (i inh ) input current of the digital input c s (off) ?off? switch source capacitance. measured with reference to ground. c d , c s (on) ?on? switch capacitance. measured with reference to ground. c in digital input capacitance t on delay time measured between the 50% and 90% points of the digital inputs and the switch ?on? condition. t off delay time measured between the 50% and 90% points of the digital input and the switch ?off? condition. t on ( en ) delay time between the 50% and 90% points of the en digital input and the switch ?on? condition. t off ( en ) delay time between the 50% and 90% points of the en digital input and the switch ?off? condition. t open ?off? time measured between the 80% points of both switches when switching from one address state to another. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an ?off? switch. crosstalk a me asure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. on response the frequency response of the ?on? switch insertion loss the loss due to the on resistance of the switch. terminology a
rev. adg786/adg788 C7C v d , v s , drain or source voltage ? v 8 0 1234 7 6 5 4 3 2 1 0 on resistance ? t a = 25 c v ss = 0v v dd = 4.5v v dd = 5.5v v dd = 3.3v v dd = 2.7v 5 tpc 1. on resistance as a function of v d (v s ) for single supply v d , v s , drain or source voltage ? v 00.5 7 6 5 4 3 2 1 0 on resistance ? 1.0 1.5 2.0 2.5 3.0 8 +25 c ?40 c +85 c v dd = 3v v ss = 0v tpc 4. on resistance as a function of v d (v s ) for different temperatures, single supply v s , (v d = v dd ?v s )? v 0.10 00.5 current ? na v dd = 3v v ss = gnd t a = 25 c i s , i d (on), v d = v s i s (off) 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 1.0 1.5 2.0 2.5 3.0 tpc 7. leakage currents as a function of v d (v s ) v d , v s , drain or source voltage ? v 8 ?3 ?2 ?1 0 2 7 6 5 4 3 2 1 0 on resistance ? t a = 25 c v dd = +2.5v v ss = ?2.5v 3 1 tpc 2. on resistance as a function of v d (v s ) for dual supply v d , v s , drain or source voltage ? v 8 ?3 ?2 ?1 0 2 7 6 5 4 3 2 1 0 on resistance ? v dd = +2.5v v ss = ?2.5v 3 ?40 c 1 +85 c +25 c tpc 5. on resistance as a function of v d (v s ) for different temperatures , dual supply v s , (v d = v dd ?v s )? v 0.15 ?3 ?2 current ? na v dd = +2.5v v ss = ?2.5v t a = 25 c i s (off) 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?10123 i s , i d (on), v d = v s tpc 8. leakage currents as a function of v d (v s ) typical performance characteristics ? v d , v s , drain or source voltage ? v 8 02 7 6 5 4 3 2 1 0 on resistance ? v dd = 5v v ss = 0v 3 ?40 c 1 +85 c +25 c 45 tpc 3. on resistance as a function of v d (v s ) for different temperatures, single supply v s , (v d = v dd ?v s )? v 0.10 0123 5 current ? na v dd = 5v v ss = gnd t a = 25 c 4 i s , i d (on), v d = v s i s (off) 0.05 0 ?0.05 ?0.10 ?0.15 tpc 6. leakage currents as a function of v d (v s ) temperature ? c 0.25 5 current ? na v dd = +2.5v v ss = ?2.5v v d = +2.25v/?1.25v v s = ?1.25v/+2.25v v dd = 5v v ss = gnd v d = 4.5v/1.0v v s = 1.0v/4.5v i s , i d (on) i s (off) 0.20 0.15 0.10 0.05 0 ?0.05 20 35 50 65 80 ?0.10 tpc 9. leakage currents as a function of temperature a
rev. adg786/adg788 C8C temperature ? c 0.25 5 current ? na v dd = 3v v ss = gnd v d = 2.7v/1v v s = 1v/2.7v i s , i d (on) i s (off) 0.20 0.15 0.10 0.05 0 ?0.05 20 35 50 65 80 ?0.10 tpc 10. leakage currents as a function of temperature v ss = 3v v dd = gnd v dd = +2.5v v ss = ?2.5v v dd = 5v v ss = gnd t a = 25 c frequency ? khz 10m 0.1 current ? a 1m 100 10 1 100n 10n 1 10 100 1000 10000 tpc 13. input current, i dd vs. switching frequency voltage ? v ?3 ?2 20 10 0 ?10 q inj ? pc ?1 0 1 2 3 30 t a = 25 c v dd = 5v v ss = gnd v dd = +2.5v v ss = ?2.5v v dd = 3v v ss = gnd 45 tpc 16. charge injection vs. source voltage temperature ? c 40 ?20 time ? ns 35 30 25 20 15 10 020406080 0 v ss = gnd t on , v dd = 3v t off , v dd = 3v t on , v dd = 5v t off , v dd = 5v 5 tpc 11. t on /t off times vs. temperature frequency ? hz 0 30k attenuation ? db ?20 ?40 ?60 ?80 ?90 ?100 100k 1m 10m 100m ?70 ?50 ?30 ?10 v dd = 5v t a = 25 c tpc 14. off isolation vs. frequency frequency ? h z 0 10m 10k ?4 ?2 100k 1m 100m ?6 on response ? db ?8 ?10 ?12 ?14 ?16 v dd = 5v t a = 25 c tpc 12. on response vs. frequency frequency ? hz 0 30k attenuation ? db ?20 ?40 ?60 ?80 ?90 100k 1m 10m 100m v dd = 5v t a = 25 c ?70 ?50 ?30 ?10 tpc 15. crosstalk vs. frequency a
rev. adg786/adg788 C9C i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance test circuits v d i s (off) sd v s a test circuit 2. i s (off) i d (on) sd a v d nc nc = no connect test circuit 3. i d (on) s1a d1 vs1b in/ en gnd r l 300 c l 35pf v out v dd v dd 0.1 f s1b vs1a vss v ss 0.1 f t on 90% 90% 50% 50% address drive v out vs1b vs1a t off test circuit 4. switching times, t on , t off 3v 50% output 50% t on ( en ) 0.9v 0 0v 0v enable drive (v in ) 0.9v 0 v o t off ( en ) a2 v o d1 v s a1 a0 en gnd adg786 s1a s1b v in 50 r l 300 c l 35pf v dd v ss v ss v dd 0.1 f test circuit 5. enable delay, t on ( en ), t off ( en ) v out d1 v s gnd adg786/ adg788 sa sb v in 50 address * * a0, a1, a2 for adg786, in1-4 for adg788 v ss 0.1 f v ss v dd v dd 0.1 f r l 300 c l 35pf address 3v v out t open 80% 80% 0v v s test circuit 6. break-before-make delay, t open a
rev. adg786/adg788 C10C * in1?4 for adg734 gnd v dd adg786/ adg788 v out c l 1nf v s r s d s v dd v ss v ss v in en * v out 3v v out logic input (v in ) q inj = c l v out 0v test circuit 7. charge injection v s v out 50 network analyzer r l 50 in gnd v in s d 50 off isolation = 20 log v out v s v dd 0.1 f v dd v ss 0.1 f v ss test circuit 8. off isolation channel-to-channel crosstalk = 20 log gnd v dd 0.1 f v dd v ss 0.1 f v ss sa d sb v s v out network analyzer r l 50 in v out v s 50 r 50 test circuit 9. channel-to-channel crosstalk power supply sequencing when using cmos devices, care must be taken to ensure cor- rect power supply sequencing. incorrect sequencing can result in the device being subjected to stresses beyond those maximum ratings listed in the data sheet. digital and analog inputs should be applied to the device after supplies and ground. in dual sup- ply applications, if digital and analog inputs may be applied prior to v dd and v ss supplies, the addition of a schottky diode connected between v ss and gnd will ensure that the device powers on correctly. for single supply applications, v ss should be tied to gnd as close to the device as possible. v s v out 50 network analyzer r l 50 in gnd v in s d insertion loss = 20 log v out with switch v out without switch v dd 0.1 f v dd v ss 0.1 f v ss test circuit 10. bandwidth a
adg786/adg788 rev. a | page 11 outline dimensions 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-1) dimensions shown in inches and (mm) ordering guide model 1, 2 temperature range package description package option adg786bcpz C40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adg786bcpz-reel7 C40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adg786wbcpz-reel7 C40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 ADG788BCPZ C40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 ADG788BCPZ-reel C40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 ADG788BCPZ-reel7 C40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 eval-adg788ebz evaluation board 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the adg786w models are available with controlled manufacturing to support the quality and reliability requirements of automotiv e applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. revision history 8/12rev. 0 to rev. a updated outline dimensions ........................................................ 11 changes to ordering guide ........................................................... 11 added automotive products section ........................................... 11 7/01revision 0: initial version 3.75 bcs sq compliant to jedec standards mo-220-vggd-1 1 0.50 bsc p i n 1 i n d i c a t o r 0.75 0.60 0.50 top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 2.25 2.10 sq 1.95 20 6 16 10 11 15 5 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 04-09-2012-b bottom view exposed pad 4.10 4.00 sq 3.90 ?2001C2012 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02381-0-8/12(a)

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